Statistical variability and reliability and the impact on corresponding 6T-SRAM cell design for a 14-nm node SOI FinFET technology

Wang, X., Cheng, B., Brown, A. R., Millar, C., Kuang, J. B., Nassif, S. and Asenov, A. (2013) Statistical variability and reliability and the impact on corresponding 6T-SRAM cell design for a 14-nm node SOI FinFET technology. IEEE Design and Test, 30(6), pp. 18-28. (doi: 10.1109/MDAT.2013.2266395)

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Publisher's URL: http://dx.doi.org/10.1109/MDAT.2013.2266395

Abstract

This paper presents an evaluation of 14-nm SOI FinFET CMOS SRAM codesign techniques in the presence of statistical variability and reliability impact. As statistical variability sources random discrete dopants, gate-edge roughness, fi-edge roughness, metal-gate granularity and random interface trapped charges in N/PBTI are considered.

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Millar, Dr Campbell and Wang, Dr Xingsheng and Asenov, Professor Asen and Brown, Mr Andrew and Cheng, Dr Binjie
Authors: Wang, X., Cheng, B., Brown, A. R., Millar, C., Kuang, J. B., Nassif, S., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:IEEE Design and Test
Publisher:Institute of Electrical and Electronics Engineers
ISSN:2168-2356

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
443791Atomic scale simulation of nanoelectronic devicesAsen AsenovEngineering & Physical Sciences Research Council (EPSRC)EP/E038344/1ENG - ENGINEERING ELECTRONICS & NANO ENG