Rogers, E. and Li, Y. (1988) Systolic array based concurrent processing for real-time high performance control. In: IEEE Decision and Control, 1988, Austin, TX, USA, 7-9 Dec 1988, pp. 2236-2237. (doi: 10.1109/CDC.1988.194729)
Full text not currently available from Enlighten.
Publisher's URL: http://dx.doi.org/10.1109/CDC.1988.194729
Abstract
Concurrent processing techniques are applied to real-time high-performance control problems. In particular, four shortest-latency systolic array architectures are developed for controller implementation in such problems at word level. A technique termed `M-expanded pipelining' is used to pipeline these architectures to an arbitrary deeper level. Some preliminary results concerning the expected performance of these architectures are presented.
Item Type: | Conference Proceedings |
---|---|
Status: | Published |
Refereed: | Yes |
Glasgow Author(s) Enlighten ID: | Li, Professor Yun |
Authors: | Rogers, E., and Li, Y. |
Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
College/School: | College of Science and Engineering > School of Engineering > Systems Power and Energy |
University Staff: Request a correction | Enlighten Editors: Update this record