Unified compact modelling strategies for process and statistical variability in 14-nm node DG FinFETs

Wang, X., Cheng, B., Brown, A.R., Millar, C., Alexander, C., Reid, D., Kuang, J.B., Nassif, S. and Asenov, A. (2013) Unified compact modelling strategies for process and statistical variability in 14-nm node DG FinFETs. In: 18th International Conference on Simulation of Semiconductor Processes and Devices: SISPAD 2013, Glasgow, UK, 3-5 Sep 2013, pp. 139-142.

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Publisher's URL: http://www.sispad2013.org/

Abstract

This paper presents a principal component analysis (PCA)-based unified compact modelling strategy for processinduced and statistical variability in 14-nm double gate SOI FinFET technology. There is strong interplay between process and statistical variability in FinFET technology and failure to capture the correlations between them can lead to an inaccurate estimation of overall statistical variability with errors of up to 30%. Therefore a new unified compact modelling strategy for variability, based on comprehensive atomistic simulations within the CD corner space, is presented. First, an extended uniform compact model is built to capture CD process variation using a set of parameters, and then statistical variability is extracted using another small set of ‘statistical’ parameters. Later, the response of the extracted statistical parameters over the CD space is characterised, and finally used in a PCA method to generate the unified compact models capturing both process and statistical variability over the whole CD variation space.

Item Type:Conference Proceedings
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Alexander, Dr Craig and Millar, Dr Campbell and Brown, Mr Andrew and Cheng, Dr Binjie and Wang, Dr Xingsheng and Asenov, Professor Asen
Authors: Wang, X., Cheng, B., Brown, A.R., Millar, C., Alexander, C., Reid, D., Kuang, J.B., Nassif, S., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering

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