Moadeli, M., Shahrabi, A., Vanderbauwhede, W. and Maji, P. (2010) An analytical performance model for the Spidergon NoC with virtual channels. Journal of Systems Architecture, 56(1), 16 - 26. (doi: 10.1016/j.sysarc.2009.10.002)
Full text not currently available from Enlighten.
Abstract
The Spidergon Network-on-Chip (NoC) was proposed to address the demand for a fixed and optimized communication infrastructure for cost-effective multi-processor Systems-on-Chip (MPSoC) development. To deal with the increasing diversity in quality of service requirements of SoC applications, the performance of this architecture needs to be improved. Virtual channels have traditionally been employed to enhance the performance of the interconnect networks. In this paper, we present analytical models to evaluate the message latency and network throughput in the Spidergon NoC and investigate the effect of employing virtual channels. Results obtained through simulation experiments show that the model exhibits a good degree of accuracy in predicting average message latency under various working conditions. Moreover an FPGA implementation of the Spidergon has been developed to provide an accurate analysis of the cost of employing virtual channels in this architecture.
Item Type: | Articles |
---|---|
Keywords: | Spidergon, Network-on-Chip, FPGA |
Status: | Published |
Refereed: | Yes |
Glasgow Author(s) Enlighten ID: | Vanderbauwhede, Professor Wim and Moadeli, Mr Mahmoud |
Authors: | Moadeli, M., Shahrabi, A., Vanderbauwhede, W., and Maji, P. |
College/School: | College of Science and Engineering > School of Computing Science |
Research Group: | Embedded, Networked and Distributed Systems |
Journal Name: | Journal of Systems Architecture |
Publisher: | Elsevier B.V. |
ISSN: | 1383-7621 |
ISSN (Online): | 1873-6165 |
University Staff: Request a correction | Enlighten Editors: Update this record