Interplay between process-induced and statistical variability in 14-nm CMOS technology double-gate SOI FinFETs

Wang, X., Cheng, B., Brown, A.R., Millar, C., Kuang, J.B., Nassif, S. and Asenov, A. (2013) Interplay between process-induced and statistical variability in 14-nm CMOS technology double-gate SOI FinFETs. IEEE Transactions on Electron Devices, 60(8), pp. 2485-2492. (doi: 10.1109/TED.2013.2267745)

Full text not currently available from Enlighten.

Abstract

This paper presents a comprehensive simulation study of the interactions between long-range process and short-range statistical variability in a 14-nm technology node silicon-on-insulator FinFET. First, the individual and combined impact of the relevant variability sources, including random discrete dopants, fin line edge roughness (LER), gate LER, and metal gate granularity are studied for the nominal 20-nm physical gate-length FinFET design. This is followed by a comprehensive study of the interactions of the channel length, fin width and fin height systematic process variations with the combined statistical variability sources. The simulations follow a $3times 3times 3=27$ experiment design that covers the process variability space, and 1000 statistical simulations are carried out at each node of the experiment. Both metal-gate-first and metal-gate-last technologies are considered. It is found that statistical variability is significantly dependent on the process-induced variability. The applicability of the Pelgrom law to the FinFET statistical variability, subject to long-range process variations, is also examined. Mismatch factor is strongly dependent on the process variations.

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Millar, Dr Campbell and Wang, Dr Xingsheng and Asenov, Professor Asen and Brown, Mr Andrew and Cheng, Dr Binjie
Authors: Wang, X., Cheng, B., Brown, A.R., Millar, C., Kuang, J.B., Nassif, S., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:IEEE Transactions on Electron Devices
Publisher:Institute of Electrical and Electronics Engineers
ISSN:0018-9383
ISSN (Online):1557-9646

University Staff: Request a correction | Enlighten Editors: Update this record

Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
443791Atomic scale simulation of nanoelectronic devicesAsen AsenovEngineering & Physical Sciences Research Council (EPSRC)EP/E038344/1ENG - ENGINEERING ELECTRONICS & NANO ENG