Statistical variability in 14-nm node SOI FinFETs and its impact on corresponding 6T-SRAM cell design

Wang, X., Cheng, B., Brown, A.R., Miller, C. and Asenov, A. (2012) Statistical variability in 14-nm node SOI FinFETs and its impact on corresponding 6T-SRAM cell design. In: ESSDERC2012: European Solid-State Device Research Conference 2012, Bordeaux, France, 17-21 Sep 2012, pp. 113-116. (doi: 10.1109/ESSDERC.2012.6343346)

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Publisher's URL: http://dx.doi.org/10.1109/ESSDERC.2012.6343346

Abstract

This paper presents a comprehensive statistical variability study of 14-nm technology node SOI FinFET which is optimized based on extensive exploration of TCAD design space. The variability sources, including random discrete dopants, gate and fin edge roughness, and possible metal gate granularity, are simulated and examined in term of their impacts on device parameters. The impact of intrinsic parameter fluctuations on a high density SOI FinFET 6T-SRAM cell is also investigated.

Item Type:Conference Proceedings
Additional Information:ISBN: 9781467317078
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Brown, Mr Andrew and Cheng, Dr Binjie and Wang, Dr Xingsheng and Asenov, Professor Asen
Authors: Wang, X., Cheng, B., Brown, A.R., Miller, C., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Research Group:Device Modelling Group

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
501811ENIAC MOdeling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems (MODERN)Asen AsenovEngineering & Physical Sciences Research Council (EPSRC)EP/G04130X/1ENG - ENGINEERING ELECTRONICS & NANO ENG
561641Statistical Design and Verification of Analogue Systems (StatDes)Asen AsenovScottish Funding Council (SFC)HR10018ENG - ENGINEERING ELECTRONICS & NANO ENG