Deep sub-micron and self-aligned flatband III–V MOSFETs

Hill, R.J.W. et al. (2009) Deep sub-micron and self-aligned flatband III–V MOSFETs. In: Device Research Conference, 2009 (DRC 2009), University Park, PA, USA, 22-24 Jun 2009, pp. 251-252. (doi:10.1109/DRC.2009.5354900)

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Abstract

In conclusion, this paper reports a number of significant developments in III-V MOSFET devices. Retaining a subthreshold slope of 60-70 mV/decade for gate lengths down to 100 nm with an EOT of 3.4 nm shows for the first time that the flatband mode device architecture is tolerant to short channel effects. In addition, a generic silicon compatible process flow for the realization of fully self-aligned III-V MOSFETs has been demonstrated and shown capable of realizing 100 nm gate length enhancement mode devices

Item Type:Conference Proceedings
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Longo, Dr Paolo and Li, Dr Xu and Zhou, Dr Haiping and Thayne, Professor Iain and Macintyre, Dr Douglas and Thoms, Dr Stephen and Asenov, Professor Asen and Hill, Mr Richard and Craven, Professor Alan and Stanley, Professor Colin and Moran, Dr David and Holland, Dr Martin
Authors: Hill, R.J.W., Li, X., Zhou, H., Macintyre, D.S., Thoms, S., Holland, M.C., Longo, P., Moran, D.A.J., Craven, A.J., Stanley, C.R., Asenov, A., Droopad, R., Passlack, M., and Thayne, I.G.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering

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