Ternent, G. and Paul, D. (2012) SPICE modeling of the scaling of resonant tunneling diodes and the effects of sidewall leakage. IEEE Transactions on Electron Devices, 59(12), pp. 3555-3560. (doi: 10.1109/TED.2012.2219867)
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Publisher's URL: http://dx.doi.org/10.1109/TED.2012.2219867
Abstract
Si/SiGe and AlGaAs/GaAs resonant tunneling diodes (RTDs) are realized using a self-aligned fabrication process with dimensions ranging from 50 $muhbox{m}$ down to 30 nm. Using these devices, scaling rules are developed and incorporated into a modified SPICE model. The depletion width and the sidewall current are extracted from the model. The results confirm that the parasitic sidewall current is responsible for the reduction in peak-to-valley current ratio (PVCR) in small-diameter RTDs. A new device layout is demonstrated to significantly reduce the sidewall current for optimum nanoscale performance. Improvements in the PVCRs are demonstrated by this approach.
Item Type: | Articles |
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Status: | Published |
Refereed: | Yes |
Glasgow Author(s) Enlighten ID: | Ternent, Dr Gary and Paul, Professor Douglas |
Authors: | Ternent, G., and Paul, D. |
College/School: | College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering |
Journal Name: | IEEE Transactions on Electron Devices |
ISSN: | 0018-9383 |
ISSN (Online): | 1557-9646 |
Published Online: | 01 December 2012 |
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