Optimisation and parallelism in synchronous digital circuit simulators

Chimeh, M. K., Hall, C. and O'Donnell, J. (2012) Optimisation and parallelism in synchronous digital circuit simulators. In: IEEE International Conference on Computational Science and Engineering, Nicosia, 5-7 Dec. 2012, pp. 94-101. (doi: 10.1109/ICCSE.2012.23)

70983.pdf - Accepted Version



Digital circuit simulation often requires a large amount of computation, resulting in long run times. We consider several techniques for optimising a brute force synchronous circuit simulator: an algorithm using an event queue that avoids recalculating quiescent parts of the circuit, a marking algorithm that is similar to the event queue but that avoids a central data structure, and a lazy algorithm that avoids calculating signals whose values are not needed. Two target architectures for the simulator are used: a sequential CPU, and a parallel GPGPU. The interactions between the different optimisations are discussed, and the performance is measured while the algorithms are simulating a simple but realistic scalable circuit.

Item Type:Conference Proceedings
Additional Information:ISBN: 9781467351652
Glasgow Author(s) Enlighten ID:O'Donnell, Dr John and Hall, Dr Cordelia
Authors: Chimeh, M. K., Hall, C., and O'Donnell, J.
Subjects:Q Science > QA Mathematics > QA75 Electronic computers. Computer science
College/School:College of Science and Engineering > School of Computing Science
Research Group:ENDS
Copyright Holders:Copyright © 2012 The Authors

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