Silicon nanowire devices with widths below 5nm

Mirza, M.M. , Velha, P., Ternent, G., Zhou, H.P., Docherty, K.E. and Paul, D.J. (2012) Silicon nanowire devices with widths below 5nm. In: 12th IEEE Conference on Nanotechnology, Birmingham, UK, 20-23 Aug 2012, (doi:10.1109/NANO.2012.6322005)

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Abstract

This paper describes a robust process for the fabrication of highly doped Silicon-On-Insulator nanowires and devices. The process uses electron-beam lithography, low-damage dry etch and controlled thermal oxidation to deliver consistent, reproducible and reliably nanowires of nominal widths from 100 nm down to sub-5 nm etched to a depth of 55 nm in silicon. Initial electrical measurements indicate metallic behavior for the widest wires and below a particular width, the wires become depleted showing electrical behaviour consistent with Coulomb blockade at room temperature.

Item Type:Conference Proceedings
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Mirza, Dr Muhammad M A and Zhou, Dr Haiping and Paul, Professor Douglas and Ternent, Dr Gary
Authors: Mirza, M.M., Velha, P., Ternent, G., Zhou, H.P., Docherty, K.E., and Paul, D.J.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering

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