Gallium oxide and gadolinium gallium oxide insulators on Si δ-doped GaAs/AlGaAs heterostructures

Paterson, G.W. , Longo, P., Wilson, J.A., Craven, A.J., Long, A.R., Thayne, I.G., Passlack, M. and Droopad, R. (2008) Gallium oxide and gadolinium gallium oxide insulators on Si δ-doped GaAs/AlGaAs heterostructures. Journal of Applied Physics, 104(10), p. 103719. (doi:10.1063/1.3029661)

Paterson, G.W. , Longo, P., Wilson, J.A., Craven, A.J., Long, A.R., Thayne, I.G., Passlack, M. and Droopad, R. (2008) Gallium oxide and gadolinium gallium oxide insulators on Si δ-doped GaAs/AlGaAs heterostructures. Journal of Applied Physics, 104(10), p. 103719. (doi:10.1063/1.3029661)

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Publisher's URL: http://dx.doi.org/10.1063/1.3029661

Abstract

Test devices have been fabricated on two specially grown GaAs/AlGaAs wafers with 10 nm thick gate dielectrics composed of either Ga<sub>2</sub>O<sub>3</sub> or a stack of Ga<sub>2</sub>O<sub>3</sub> and Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub>. The wafers have two GaAs transport channels either side of an AlGaAs barrier containing a Si delta-doping layer. Temperature dependent capacitance-voltage (C-V) and current-voltage (I-V) studies have been performed at temperatures between 10 and 300 K. Bias cooling experiments reveal the presence of DX centers in both wafers. Both wafers show a forward bias gate leakage that is by a single activated channel at higher temperatures and by tunneling at lower temperatures. When Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> is included in a stack with 1 nm of Ga<sub>2</sub>O<sub>3</sub> at the interface, the gate leakage is greatly reduced due to the larger band gap of the Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> layer. The different band gaps of the two oxides result in a difference in the gate voltage at the onset of leakage of ~3 V. However, the inclusion of Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> in the gate insulator introduces many oxide states (≤4.70Ã�Â�10<sup>12</sup> cm<sup>âÂ�Â�2</sup>). Transmission electron microscope images of the interface region show that the growth of a Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> layer on Ga<sub>2</sub>O<sub>3</sub> disturbs the well ordered Ga<sub>2</sub>O<sub>3</sub>/GaAs interface. We therefore conclude that while including Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> in a dielectric stack with Ga<sub>2</sub>O<sub>3</sub> is necessary for use in device applications, the inclusion of Gd decreases the quality of the Ga<sub>2</sub>O<sub>3</sub>/GaAs interface and near interface region by introducing roughness and a large number of defect states.

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Thayne, Professor Iain and Wilson, Dr James and Longo, Dr Paolo and Long, Professor Andrew and Craven, Professor Alan and Paterson, Dr Gary
Authors: Paterson, G.W., Longo, P., Wilson, J.A., Craven, A.J., Long, A.R., Thayne, I.G., Passlack, M., and Droopad, R.
Subjects:Q Science > QC Physics
College/School:College of Science and Engineering > School of Physics and Astronomy
Journal Name:Journal of Applied Physics
Publisher:American Institute of Physics
ISSN:0021-8979
ISSN (Online):1089-7550
Published Online:25 November 2008

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
358573Sub 100nm 111-V MOSFET's for Digital ApplicationsIain ThayneEngineering & Physical Sciences Research Council (EPSRC)GR/S61218/01Electronic and Nanoscale Engineering
452481Silicon compatible process modules for III-V electronic devices.Iain ThayneEngineering & Physical Sciences Research Council (EPSRC)EP/F002610/1Electronic and Nanoscale Engineering