Simulation study of dominant statistical variability sources in 32-nm high-k/metal gate CMOS

Wang, X., Roy, G., Saxod, O., Bajolet, A., Juge, A. and Asenov, A. (2012) Simulation study of dominant statistical variability sources in 32-nm high-k/metal gate CMOS. IEEE Electron Device Letters, 33(5), pp. 643-645. (doi: 10.1109/LED.2012.2188268)

Full text not currently available from Enlighten.

Abstract

Comprehensive 3-D simulations have been carried out and compared with experimental data highlighting the dominant sources of statistical variability in 32-nm high-$kappa/hbox{metal}$ gate MOSFET technology. The statistical variability sources include random discrete dopants, line edge roughness, and metal gate granularity. Their relative importance is highlighted in the numerical simulations. Excellent agreement is achieved between the simulated and measured standard deviation of the threshold voltage.

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Wang, Dr Xingsheng and Roy, Dr Gareth and Asenov, Professor Asen
Authors: Wang, X., Roy, G., Saxod, O., Bajolet, A., Juge, A., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:IEEE Electron Device Letters
Publisher:Institute of Electrical and Electronics Engineers
ISSN:0741-3106
Published Online:20 April 2012

University Staff: Request a correction | Enlighten Editors: Update this record

Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
443791Atomic scale simulation of nanoelectronic devicesAsen AsenovEngineering & Physical Sciences Research Council (EPSRC)EP/E038344/1Electronic and Nanoscale Engineering