An ultralow-resistance ultrashallow metallic source/drain contact scheme for III-V NMOS

Oxland, R. et al. (2012) An ultralow-resistance ultrashallow metallic source/drain contact scheme for III-V NMOS. IEEE Electron Device Letters, 33(4), pp. 501-503. (doi:10.1109/LED.2012.2185919)

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Abstract

We report an ultrashallow metallic source/drain (S/D) contact scheme for fully self-aligned III-V NMOS with specific contact resistivity and sheet resistance which, for the first time, demonstrate performance metrics that may be compatible with the ITRS Rext requirements for 12-nm technology generation device pitch. The record specific contact resistivity between the contact pad and metallic S/D of ρc = 2.7 ·10-9 Ω·cm2 has been demonstrated for 10 nm undoped InAs channels by forming an ultrashallow crystalline ternary NiInAs phase with Rsh = 97 Ω/sq for a junction depth of 7 nm. The junction depth of the S/D scheme is highly controllable and atomically abrupt.

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Li, Dr Xu and Thayne, Professor Iain and Oxland, Dr Richard
Authors: Oxland, R., Chang, S.W., Li, X., Wang, S.W., Radhakrishnan, G., Priyantha, W., van Dal, M.J.H., Hsieh, C.H., Vellianitis, G., Doornbos, G., Bhuwalka, K., Duriez, B., Thayne, I., Droopad, R., Passlack, M., Diaz, C.H., and Sun, Y.C.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:IEEE Electron Device Letters
Publisher:Institute of Electrical and Electronics Engineers
ISSN:0741-3106

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