Numerical analysis of the new implant-free quantum-well CMOS: DualLogic approach

Benbakhti, B. et al. (2011) Numerical analysis of the new implant-free quantum-well CMOS: DualLogic approach. Solid-State Electronics, 63(1), pp. 14-18. (doi: 10.1016/j.sse.2011.05.006)

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The research into alternative channel materials to improve CMOS performance is a rapidly growing area of research. III–V and Ge based MOSFETs offer attractive possibilities for a high performance and low power circuit implementation. Here, we report a global performance analysis of future DualLogic CMOS based on the new, Implant-FreeQuantum-Well device architecture for both III–V nMOSFETs and Ge pMOSFETs. The III–V nMOSFETs are optimised to achieve low leakage, high performance and its performance is evaluated using ensemble Monte Carlo simulations. A similar approach is adopted for the Ge pMOSFETs. In addition, the impact of the interface states density on the output characteristics is also studied. Finally, the timing performance of the DualLogic CMOS is evaluated using mixed mode TCAD and circuit simulations.

Item Type:Articles
Glasgow Author(s) Enlighten ID:Towie, Dr Ewan and Wang, Dr Xingsheng and Asenov, Professor Asen and Benbakhti, Dr Brahim and Riddet, Mr Craig and Kalna, Dr Karol
Authors: Benbakhti, B., Chan, K., Towie, E., Kalna, K., Riddet, C., Wang, X., Eneman, G., Hellings, G., De Meyer, K., Meuris, M., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Solid-State Electronics
ISSN (Online):1879-2405
Published Online:25 June 2011

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