Implementation of the density gradient quantum corrections for 3-D simulations of multigate nanoscaled transistors

Garcia-Loureiro, A.J., Seoane, N., Aldegunde, M., Valin, R., Asenov, A. , Martinez, A. and Kalna, K. (2011) Implementation of the density gradient quantum corrections for 3-D simulations of multigate nanoscaled transistors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(6), pp. 841-851. (doi: 10.1109/TCAD.2011.2107990)

Abstract

An efficient implementation of the density-gradient (DG) approach for the finite element and finite difference methods and its application in drift-diffusion (D-D) simulations is described in detail. The new, second-order differential (SOD) scheme is compatible with relatively coarse grids even for large density variations thus applicable to device simulations with complex 3-D geometries. Test simulations of a 1-D metal-oxide semiconductor diode demonstrate that the DG approach discretized using our SOD scheme can be accurately calibrated against Schrödinger-Poisson calculations exhibiting lower discretization error than the previous schemes when using coarse grids and the same results for very fine meshes. 3-D test D-D simulations using the finite element method are performed on two devices: a 10 nm gate length double gate metal-oxide-semiconductor field-effect transistor (MOSFET) and a 40 nm gate length Tri-Gate fin field-effect transistor (FinFET). In 3-D D-D simulations, the SOD scheme is able to converge to physical solutions at high voltages even if the previous schemes fail when using the same mesh and equivalent conditions. The quantum corrected D-D simulations using the SOD scheme also converge with an atomistic mesh used for the 10 nm double gate MOSFET saving computational resources and can be accurately calibrated against the results from non-equilibrium Green's functions approach. Finally, the simulated ID-VG characteristics for the 40 nm gate length Tri-Gate are in an excellent agreement with experimental data

• Item Type: Articles
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Asenov, Professor Asen and Martinez, Dr Antonio
• Authors: Garcia-Loureiro, A.J., Seoane, N., Aldegunde, M., Valin, R., Asenov, A., Martinez, A., and Kalna, K.
• Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Journal Name: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• Publisher: Institute of Electrical and Electronics Engineers
• ISSN: 0278-0070
• ISSN (Online): 1937-4151
• Published Online: 16 May 2011

Project Code	Award No	Project Name	Principal Investigator	Funder's Name	Funder Ref	Lead Dept
44379	1	Atomic scale simulation of nanoelectronic devices	Asen Asenov	Engineering & Physical Sciences Research Council (EPSRC)	EP/E038344/1	Electronic and Nanoscale Engineering