Robust Low Power Design in Nano-CMOS Technologies

Azam, T. and Cumming, D. (2010) Robust Low Power Design in Nano-CMOS Technologies. In: 2010 IEEE International Symposium on Circuits and Systems, Paris, France, 30 May - 2 June 2010, (doi: 10.1109/ISCAS.2010.5537142)

Full text not currently available from Enlighten.


Increasing variability in nano-CMOS technologies poses a major challenge for low power design. Conventional design methods add large safety margins to mitigate variability that incur high power/ performance loss. We present a sensor based design methodology that minimizes pessimistic margin, while still providing reliable circuit operation. Variation resilient sensors are embedded in our design to detect minimum supply voltage that allows low power error free operation. HSPICE simulations indicate a 42% reduction in the average power consumption under temperature variations.

Item Type:Conference Proceedings
Glasgow Author(s) Enlighten ID:Cumming, Professor David and Azam, Mr Touqeer
Authors: Azam, T., and Cumming, D.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering

University Staff: Request a correction | Enlighten Editors: Update this record