Si/Si1-xGex heterostructure field effect transistors fabricated using a low thermal budget CMOS process

Dunford, R.B., Paul, D.J. , Pepper, M., Coonan, B., Griffin, N., Redmond, G., Crean, G.M., Hollander, B. and Mantl, S. (2000) Si/Si1-xGex heterostructure field effect transistors fabricated using a low thermal budget CMOS process. Microelectronic Engineering, 53(1-4), pp. 209-212. (doi:10.1016/S0167-9317(00)00298-7)

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Abstract

Strained Si/Si0.75Ge0.25 heterostructure field effect transistors (HFETs) have been fabricated using a modified, low-thermal budget CMOS process with deposited gate oxides. Transmission electron microscopy demonstrates the integrity of the strained-Si quantum well after processing. The transconductances of the HFET devices are higher than the similarly processed Si MOSFET devices. Electrical characterisation data is presented which suggest that thinner gate oxides, higher Ge contents in the virtual substrate and optimisation of the p-type substrate doping profile will improve device performance.

Item Type:Articles
Additional Information:25th International Conference on Micro- and Nano-Engineering, Rome, Italy, 21-23 September, 1999. This work was funded by the European Community under the Esprit Microelectronics Advanced Research Initiative (MEL-ARI), Project No. 22987 "Silicon Quantum Integrated Circuits".
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Paul, Professor Douglas
Authors: Dunford, R.B., Paul, D.J., Pepper, M., Coonan, B., Griffin, N., Redmond, G., Crean, G.M., Hollander, B., and Mantl, S.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Research Group:Semiconductor Devices
Journal Name:Microelectronic Engineering
Publisher:Elsevier
ISSN:0167-9317
ISSN (Online):1873-5568

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