High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture

Olsen, S. H. et al. (2003) High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture. IEEE Transactions on Electron Devices, 50(9), pp. 1961-1969. (doi:10.1109/TED.2003.815603)

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Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si/sub 0.7/Ge/sub 0.3/ on an Si/sub 0.85/Ge/sub 0.15/ virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process.

Item Type:Articles
Glasgow Author(s) Enlighten ID:Paul, Professor Douglas
Authors: Olsen, S. H., O'Neill, A. G., Driscoll, L. S., Kwa, K. S. K., Chattopadhyay, S., Waite, A. M., Tang, Y. T., Evans, A. G.R., Norris, D. J., Cullis, A. G., Paul, D. J., and Robbins, D. J.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Research Group:Semiconductor Devices
Journal Name:IEEE Transactions on Electron Devices
Publisher:Institute of Electrical and Electronics Engineers
ISSN (Online):1557-9646
Published Online:26 August 2003

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