Strained-Si n-MOS surface-channel and buried Si0.7Ge0.3 compressively-strained p-MOS fabricated in a 0.25 mu m heterostructure CMOS process

Paul, D.J. et al. (2005) Strained-Si n-MOS surface-channel and buried Si0.7Ge0.3 compressively-strained p-MOS fabricated in a 0.25 mu m heterostructure CMOS process. Materials Science in Semiconductor Processing, 8(1-3), pp. 343-346. (doi:10.1016/j.mssp.2004.09.106)

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Abstract

A 0.25 μm complimentary metal oxide semiconductor (CMOS) process has been used to fabricate surface channel strained-Si n-MOS devices and buried, compressively-strained-Si0.7Ge0.3 channel p-MOS. Enhancements in performance of on-current, transconductance and mobility over bulk, relaxed Si CMOS devices are demonstrated for both n- and p-MOS devices for all gate lengths fabricated from 0.1 up to 10 μm. The performance is compared to surface channel strained-Si CMOS which is superior to the buried channel results. Possible reasons are discussed.

Item Type:Articles
Additional Information:The work was funded by EPSRC under the HMOS II programme.
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Paul, Professor Douglas
Authors: Paul, D.J., Temple, M., Olsen, S.H., O'Neill, A.G., Tang, Y.T., Waite, A.M., Cerrina, C., Evans, A.G.R., Li, X., Zhang, J., Norris, D.J., and Cullis, A.G.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Research Group:Semiconductor Devices
Journal Name:Materials Science in Semiconductor Processing
Publisher:Elsevier
ISSN:1369-8001
ISSN (Online):1873-4081
Published Online:04 November 2004

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