Doubling speed using strained Si/SiGe CMOS technology

Olsen, S.H., Temple, M., O'Neill, A.G., Paul, D.J. , Chattopadhyay, S., Kwa, K.S.K. and Driscoll, L.S. (2006) Doubling speed using strained Si/SiGe CMOS technology. Thin Solid Films, 508(1-2), pp. 338-341. (doi:10.1016/j.tsf.2005.07.347)

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Abstract

The benefit of high performance strained Si CMOS in terms of technology generations is quantified. It is shown that a 0.3 μm gate length strained Si/Si0.75Ge0.25 CMOS technology has the same gate delay as conventional technology having an effective gate length of 0.14 μm, but without the cost of re-tooling. Transconductance enhancements over conventional CMOS in excess of 200% are demonstrated for surface channel n- and p-MOSFETs using a Si0.75Ge0.25 virtual substrate without CMP and a high thermal budget process. To our knowledge these represent the best results reported to date at these dimensions.

Item Type:Articles
Additional Information:Proceedings of the 4th International Conference on Silicon Epitaxy and Heterostructures, Awaji Island, Hyogo, Japan, 23-26 May 2005
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Paul, Professor Douglas
Authors: Olsen, S.H., Temple, M., O'Neill, A.G., Paul, D.J., Chattopadhyay, S., Kwa, K.S.K., and Driscoll, L.S.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Research Group:Semiconductor Devices
Journal Name:Thin Solid Films
Publisher:Elsevier
ISSN:0040-6090
ISSN (Online):0040-6090
Published Online:18 November 2005

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