A low damage fully self-aligned gate-last process for fabricating sub-100 nm gate length enhancement mode GaAs MOSFETs

Li, X. , Bentley, S., Holland, M.C., Zhou, H., Thoms, S. , Macintyre, D.S. and Thayne, I.G. (2010) A low damage fully self-aligned gate-last process for fabricating sub-100 nm gate length enhancement mode GaAs MOSFETs. In: 54th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication, Anchorage, USA, June 2010,

Full text not currently available from Enlighten.


Item Type:Conference Proceedings
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Li, Dr Xu and Zhou, Dr Haiping and Thayne, Professor Iain and Macintyre, Dr Douglas and Thoms, Dr Stephen and Bentley, Dr Steven and Holland, Dr Martin
Authors: Li, X., Bentley, S., Holland, M.C., Zhou, H., Thoms, S., Macintyre, D.S., and Thayne, I.G.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering

University Staff: Request a correction | Enlighten Editors: Update this record