Impact of strain on the performance of high-k/metal replacement gate MOSFETs

Wang, X.S., Roy, S. and Asenov, A. (2009) Impact of strain on the performance of high-k/metal replacement gate MOSFETs. In: 10th International Conference on Ultimate Integration of Silicon, Aachen, Germany, 18-20 March 2009, pp. 289-292. (doi:10.1109/ULIS.2009.4897592)

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Abstract

This paper presents a simulation study of the impact of strain on scaled high performance pMOSFETs. The gate-last strain enhancement technique is employed in high-k/metal gate technology to fortify strain, and the underlying strain enhancement mechanism is studied. The strain contribution to performance improvement is differentiated from that due to the other beneficial aspects of the metal gate. Finally, the factors affecting device performance enhancement due to the scaling process are explored.

Item Type:Conference Proceedings
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Roy, Professor Scott and Wang, Dr Xingsheng and Asenov, Professor Asen
Authors: Wang, X.S., Roy, S., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering

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