Fabrication and performance of 50 nm T-gates for InP high electron mobility transistors

Cao, X., Thoms, S., Macintyre, D., McLelland, H., Boyd, E., Elgaid, K., Hill, R., Stanley, C.R. and Thayne, I.G. (2004) Fabrication and performance of 50 nm T-gates for InP high electron mobility transistors. Microelectronic Engineering, 73-74, pp. 818-821. (doi: 10.1016/j.mee.2004.03.058)

Full text not currently available from Enlighten.

Publisher's URL: http://dx.doi.org/10.1016/j.mee.2004.03.058

Abstract

Fifty nanometre gate length T-gates In<sub>0.52</sub>A1<sub>0.48</sub>As/In<sub>0.53</sub>Ga<sub>0.47</sub>As high electron mobility transistors (HEMTs) on a InP substrate were fabricated with high resolution electron-beam (e-beam) lithography using a novel UVIII/LOR/PMMA T-gate resist stack and with a non-selective digital wet etch gate recess technology. The reproducibility of the gate lithography depends on the substrate slope when mounted on the holder of e-beam lithography tool. This mounting effect is almost eliminated by calibrating the tool using a specially fabricated marker on the wafer instead of the holder marker as in usual. Initial devices exhibited a maximum transconductance (<i>g</i><sub>m</sub>) of 950 mS/mm and a current cut-off frequency (<i>f</i><sub>t</sub>) of 300 GHz.

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Thayne, Prof Iain and Thoms, Dr Stephen and Stanley, Professor Colin and Elgaid, Dr Khaled and Macintyre, Dr Douglas
Authors: Cao, X., Thoms, S., Macintyre, D., McLelland, H., Boyd, E., Elgaid, K., Hill, R., Stanley, C.R., and Thayne, I.G.
Subjects:Q Science > QC Physics
T Technology > T Technology (General)
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
University Centres > Glasgow Materials Research Initiative
Journal Name:Microelectronic Engineering
ISSN:0167-9317

University Staff: Request a correction | Enlighten Editors: Update this record