A hardware relaxation paradigm for solving NP-hard problems

Cockshott, P., Koltes, A., O'Donnell, J., Prosser, P. and Vanderbauwhede, W. (2008) A hardware relaxation paradigm for solving NP-hard problems. In: Abramsky, S., Gelenbe, E. and Sassone, V. (eds.) Visions of Computer Science: BCS International Academic Conference, Imperial College, London, UK, 22-24 September 2008. BCS: Swindon, UK, pp. 75-86.

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Digital circuits with feedback loops can solve some instances of NP-hard problems by relaxation: the circuit will either oscillate or settle down to a stable state that represents a solution to the problem instance. This approach differs from using hardware accelerators to speed up the execution of deterministic algorithms, as it exploits stabilisation properties of circuits with feedback, and it allows a variety of hardware techniques that do not have counterparts in software. A feedback circuit that solves many instances of Boolean satisfiability problems is described, with experimental results from a preliminary simulation using a hardware accelerator.

Item Type:Book Sections
Glasgow Author(s) Enlighten ID:Cockshott, Dr William and Vanderbauwhede, Professor Wim and O'Donnell, Dr John and Prosser, Dr Patrick
Authors: Cockshott, P., Koltes, A., O'Donnell, J., Prosser, P., and Vanderbauwhede, W.
Subjects:Q Science > QA Mathematics > QA75 Electronic computers. Computer science
College/School:College of Science and Engineering > School of Computing Science

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