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Implementation of statistical characterisation and design techniques for an industrial 0.5 μm CMOS technology

Healy, S., Horan, E., McCarthy, K., Mathewson, A., Ning, Z., Rombouts, E., Vanderbauwhede, W., and Tack, M. (1999) Implementation of statistical characterisation and design techniques for an industrial 0.5 μm CMOS technology. In: ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures, 15-18 March 1999, Goteborg, Sweden. IEEE Computer Society, Piscataway, N.J., USA, pp. 227-232. ISBN 9780780352704

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Abstract

This paper presents a methodology for statistical worst-case simulation using the BSIM3v3 model within commercially available tools. Statistical techniques such as principal component analysis and Box-Behnken designs are used to generate a subset of models which reflect the variation of measured device performance. These worst-case corners can be used in circuit simulation to account for the effects of statistical fluctuation on circuit performance. An indication of key process parameters that need to be monitored and controlled is also provided.

Item Type:Book Section
Status:Published
Glasgow Author(s):Vanderbauwhede, Dr Wim
Authors: Healy, S., Horan, E., McCarthy, K., Mathewson, A., Ning, Z., Rombouts, E., Vanderbauwhede, W., and Tack, M.
Subjects:Q Science > QA Mathematics > QA75 Electronic computers. Computer science
College/School:College of Science and Engineering > School of Computing Science
Publisher:IEEE Computer Society

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