Separation of data flow and control flow in reconfigurable multi-core SoCs using the gannet service-based architecture

Vanderbauwhede, W. (2007) Separation of data flow and control flow in reconfigurable multi-core SoCs using the gannet service-based architecture. In: Arslan, T. (ed.) Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 5-8 Aug. 2007, Edinburgh, UK. IEEE Computer Society: Piscataway, N.J., USA, pp. 326-333. ISBN 9780769528663 (doi:10.1109/AHS.2007.97)

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This paper presents a mechanism for the separation of control and dataflow in NoC-based SoCs consisting of multiple heterogeneous reconfigurable IP cores. This mechanism enables full data path control by an embedded microcontroller whilst avoiding the potential communication bottleneck and without requiring centralised control over the NoC. In this work, we assume a generic SoC where data processing is performed by reconfigurable IP cores interacting through a NoC and control structures are implemented on a microcontroller. The proposed mechanism employs a service-based SoC architecture (the Gannet architecture) where the control services are implemented on a Virtual Machine and IP cores acquire service behaviour through the use of a generic data marshalling and interfacing circuit. The paper aims at demonstrating how concepts from functional programming language and dataflow machine research can be applied to address the challenges faced in the design of reconfigurable heterogeneous multi-core SoCs. The presented work is theoretical in nature but is explained by example without formal analysis and notations.

Item Type:Book Sections
Glasgow Author(s) Enlighten ID:Vanderbauwhede, Professor Wim
Authors: Vanderbauwhede, W.
Subjects:Q Science > QA Mathematics > QA75 Electronic computers. Computer science
College/School:College of Science and Engineering > School of Computing Science
Publisher:IEEE Computer Society

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
389341A novel service-based system on a chip architecture using on chip networks with smart packets and dynamically reconfigurable logicWim VanderbauwhedeEngineering & Physical Sciences Research Council (EPSRC)GR/T03239/01COM - COMPUTING SCIENCE