A coarse-grained dynamically reconfigurable MAC processor for power-sensitive multi-standard devices

Nabi, S.W., Wells, C.C. and Vanderbauwhede, W. (2008) A coarse-grained dynamically reconfigurable MAC processor for power-sensitive multi-standard devices. In: 2008 IEEE International SOC Conference, 17-20 Sept. 2008, Newport Beach, CA, USA. IEEE Computer Society: Piscataway, N.J., USA, p. 151. ISBN 9781424425969 (doi:10.1109/SOCC.2008.4641500)

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We have designed a coarse-grained, dynamically reconfigurable architecture, specifically for implementing the wireless MAC layer in consumer hand-held devices. The dynamically reconfigurable MAC Processor is a SoC architecture that uses a reconfigurable hardware co-processor to delegate critical tasks. The co-processor can reconfigure packet-by-packet, handling upto 3 data streams of different protocols concurrently. We present results of simulations involving transmission and reception of packets, showing that the platform concurrently handles three protocol streams, reconfigures dynamically, yet meets and exceeds the protocol timing constraints, all at a moderate frequency. Thus we show that this architecture is capable of replacing up to three MAC processors in a wireless device. Its heterogeneous and coarse-grained functional units, requirements of limited connectivity between these units, and the idle time of hardware resources promise a very modest power-consumption, suitable for mobile devices.

Item Type:Book Sections
Glasgow Author(s) Enlighten ID:Vanderbauwhede, Professor Wim and Wells, Dr Cade
Authors: Nabi, S.W., Wells, C.C., and Vanderbauwhede, W.
Subjects:Q Science > QA Mathematics > QA75 Electronic computers. Computer science
College/School:College of Science and Engineering > School of Computing Science
Publisher:IEEE Computer Society

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