Quarc: a high-efficiency network on-chip architecture

Moadeli, M., Maji, P. and Vanderbauwhede, W. (2009) Quarc: a high-efficiency network on-chip architecture. In: International Conference on Advanced Information Networking and Applications, 2009. AINA '09, Bradford, UK, 26-29 May 2009, pp. 98-105. ISBN 9781424440009 (doi:10.1109/AINA.2009.64)

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Publisher's URL: http://dx.doi.org/10.1109/AINA.2009.64

Abstract

The novel Quarc NoC architecture, inspired by the Spidergon scheme is introduced as a NoC architecture that is highly efficient in performing collective communication operations including broadcast and multicast. The efficiency of the Quarc architecture is achieved through balancing the traffic which is the result of the modifications applied to the topology and the routing elements of the Spidergon NoC. This paper provides an ASIC implementation of both architectures using UMCpsilas 0.13 mum CMOS technology and demonstrates an analysis and comparison of the cost and performance between the Quarc and the Spidergon NoCs.

Item Type:Conference Proceedings
Additional Information:Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Moadeli, Mr Mahmoud and Vanderbauwhede, Professor Wim
Authors: Moadeli, M., Maji, P., and Vanderbauwhede, W.
Subjects:Q Science > QA Mathematics > QA75 Electronic computers. Computer science
College/School:College of Science and Engineering > School of Computing Science
Publisher:IEEE Computer Society
ISBN:9781424440009
Copyright Holders:Copyright © 2009 IEEE
First Published:First published in Proceedings of International Conference on Advanced Information Networking and Applications, 2009. AINA '09 : 98-105
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher.

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
389341A novel service-based system on a chip architecture using on chip networks with smart packets and dynamically reconfigurable logicWim VanderbauwhedeEngineering & Physical Sciences Research Council (EPSRC)GR/T03239/01COM - COMPUTING SCIENCE