A low cost reconfigurable soft processor for multimedia applications: design synthesis and programming model

Chalamalasetti, S.R., Vanderbauwhede, W. , Purohit, S. and Margala, M. (2009) A low cost reconfigurable soft processor for multimedia applications: design synthesis and programming model. In: 2009 International Conference on Field Programmable Logic and Applications. IEEE Computer Society: Piscataway, N.J., USA, pp. 534-538. ISBN 9781424438921 (doi: 10.1109/FPL.2009.5272461)

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Abstract

This paper presents an FPGA implementation of a low cost 8 bit reconfigurable processor core for media processing applications. The core is optimized to provide all basic arithmetic and logic functions required by the media processing and other domains, as well as to make it easily integrable into a 2D array. This paper presents an investigation of the feasibility of the core as a potential soft processing architecture for FPGA platforms. The core was synthesized on the entire Virtex FPGA family to evaluate its overall performance, scalability and portability. A special feature of the proposed architecture is its simple programming model which allows low level programming. Throughput results for popular benchmarks coded using the programming model and cycle accurate simulator are presented.

Item Type:Book Sections
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Status:Published
Glasgow Author(s) Enlighten ID:Vanderbauwhede, Professor Wim
Authors: Chalamalasetti, S.R., Vanderbauwhede, W., Purohit, S., and Margala, M.
Subjects:Q Science > QA Mathematics > QA75 Electronic computers. Computer science
College/School:College of Science and Engineering > School of Computing Science
Publisher:IEEE Computer Society
ISBN:9781424438921
Copyright Holders:Copyright © 2009, IEEE.
First Published:First published in 2009 International Conference on Field Programmable Logic and Applications : 534-538
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher.

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