MORA - an architecture and programming model for a resource efficient coarse grained reconfigurable processor

Chalamalasetti, S.R., Purohit, S., Margala, M. and Vanderbauwhede, W. (2009) MORA - an architecture and programming model for a resource efficient coarse grained reconfigurable processor. In: 2009 NASA/ESA Conference on Adaptive Hardware and Systems, 29 July 2009 - 1 Aug. 2009, San Francisco, CA, USA. IEEE Computer Society: Piscataway, N.J., USA, pp. 389-396. ISBN 9780769537146 (doi:10.1109/AHS.2009.37)

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Abstract

This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low cost, high throughput performance in media processing applications. A distinguishing feature of the MORA architecture is the co-design of hardware architecture and low-level programming language throughout the design cycle. The implementation details for the single MORA processor, and benchmark evaluation using a cycle accurate simulator are presented.

Item Type:Book Sections
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Status:Published
Glasgow Author(s) Enlighten ID:Vanderbauwhede, Dr Wim
Authors: Chalamalasetti, S.R., Purohit, S., Margala, M., and Vanderbauwhede, W.
Subjects:Q Science > QA Mathematics > QA75 Electronic computers. Computer science
College/School:College of Science and Engineering > School of Computing Science
Publisher:IEEE Computer Society
ISBN:9780769537146
Copyright Holders:Copyright © 2009, IEEE.
First Published:First published in Proceedings of 2009 NASA/ESA Conference on Adaptive Hardware and Systems, 29 July 2009 - 1 Aug. 2009, San Francisco, CA, USA
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher.

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