Automated instrumentation of FPGA-based systems for system-level transaction monitoring

McKechnie, P.E., Blott, M. and Vanderbauwhede, W.A. (2009) Automated instrumentation of FPGA-based systems for system-level transaction monitoring. In: 2009 International Symposium on System-on-Chip, 5-7 Oct. 2009, Tampere, Finalnd. IEEE Computer Society: Piscataway, N.J., USA, pp. 168-171. ISBN 9781424444656 (doi: 10.1109/SOCC.2009.5335653)

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Abstract

Modern FPGA-based systems are complex and difficult to verify. One approach to easing the verification problem and reducing perceived complexity is to use libraries of reusable functions. These reusable functions, known as intellectual property blocks, are commonly created as netlists or RTL components. Complex systems can be created from IP blocks by using high-level design environments. These tools define the types and semantics of component interfaces which permit systems to be debugged using system-level transaction monitoring. However, the insertion of on-chip monitoring circuitry is a manual process in FPGA design flows. In this paper we present an algorithm which exploits the high-level design environment to permit automatic instrumentation of designs. We demonstrate that the algorithm can harness existing HDL generation techniques and reduce the insertion and configuration effort required of the designer.

Item Type:Book Sections
Status:Published
Glasgow Author(s) Enlighten ID:Vanderbauwhede, Professor Wim
Authors: McKechnie, P.E., Blott, M., and Vanderbauwhede, W.A.
Subjects:Q Science > QA Mathematics > QA75 Electronic computers. Computer science
College/School:College of Science and Engineering > School of Computing Science
Publisher:IEEE Computer Society
ISBN:9781424444656

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