Moran, D.A.J., McLelland, H., Elgaid, K., Whyte, G., Stanley, C.R. and Thayne, I. (2006) 50-nm self-aligned and 'standard' T-gate InP pHEMT comparison: the influence of parasitics on performance at the 50-nm node. IEEE Transactions on Electron Devices, 53(12), pp. 2920-2925. (doi: 10.1109/TED.2006.885674)
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Publisher's URL: http://dx.doi.org/10.1109/TED.2006.885674
Abstract
Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In0.7Ga0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system
Item Type: | Articles |
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Status: | Published |
Refereed: | Yes |
Glasgow Author(s) Enlighten ID: | Thayne, Prof Iain and Stanley, Professor Colin and Moran, Professor David and Elgaid, Dr Khaled |
Authors: | Moran, D.A.J., McLelland, H., Elgaid, K., Whyte, G., Stanley, C.R., and Thayne, I. |
Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
College/School: | College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering University Centres > Glasgow Materials Research Initiative |
Journal Name: | IEEE Transactions on Electron Devices |
Publisher: | Institute of Electrical and Electronics Engineers |
ISSN: | 0018-9383 |
Copyright Holders: | Copyright © 2005 Institute of Electrical and Electronics Engineers |
First Published: | First published in IEEE Transactions on Electron Devices 53(12):2920-2925 |
Publisher Policy: | Reproduced in accordance with the copyright policy of the publisher |
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