20 Gb/s referenceless quarter-rate PLL-based clock data recovery circuit in 130 nm CMOS technology

Assaad, M. and Cumming, D.R.S. (2008) 20 Gb/s referenceless quarter-rate PLL-based clock data recovery circuit in 130 nm CMOS technology. In: Mixed Design of Integrated Circuits and Systems, 2008. MIXDES 2008. 15th International Conference on, Poznan, Poland, 19-21 June, 2008, pp. 147-150.

Assaad, M. and Cumming, D.R.S. (2008) 20 Gb/s referenceless quarter-rate PLL-based clock data recovery circuit in 130 nm CMOS technology. In: Mixed Design of Integrated Circuits and Systems, 2008. MIXDES 2008. 15th International Conference on, Poznan, Poland, 19-21 June, 2008, pp. 147-150.

Full text not currently available from Enlighten.

Abstract

This paper describes the design and transistor level simulation of a novel architecture of PLL-based clock and data recovery (PLL-CDR) circuit. The proposed PLL-CDR is a referenceless quarter-rate design that receives data at 20 Gb/s rate whereas its internal circuits work at 5 GHz frequency rate. This proposed architecture utilizes a quarter-rate early-late type phase detector (ELPD), a quarter-rate digital quadricorrelator frequency detector (DQFD) and a quarter-rate ring type voltage-controlled oscillator (VCO). The simulation results at 20 Gb/s data rate show that the quarter-rate I'LL-based CDR is a functional concept. The suggested chip design is realized in UMC 130 nm CMOS technology and occupies an area of 920 mu m x 315 mu m. The circuit's power dissipation excluding the output buffers is about 97 mW at a supply voltage of 1.2V according to the transistor level simulation results

Item Type:Conference Proceedings
Additional Information:Isbn: 9788392263272
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Cumming, Professor David
Authors: Assaad, M., and Cumming, D.R.S.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering

University Staff: Request a correction | Enlighten Editors: Update this record