An analytical performance model for the Spidergon NoC

Moadeli, M., Sharabi, A., Vanderbauwhede, W.A. and Ould-Khaoua, M. (2007) An analytical performance model for the Spidergon NoC. In: 21st Annual Conference on Advanced Networking and Applications, 2007. AINA '07, Niagra Falls, Ontario, Canada, 21-23 May 2007, pp. 1014-1021. (doi:10.1109/AINA.2007.31)



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Networks on chip (NoC) emerged as a promising alternative to bus-based interconnect networks to handle the increasing communication requirements of the large systems on chip. Employing an appropriate topology for a NoC is of high importance mainly because it typically trade-offs between cross-cutting concerns such as performance and cost. The spidergon topology is a novel architecture which is proposed recently for NoC domain. The objective of the spidergon NoC has been addressing the need for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [7]. In this paper we analyze the traffic behavior in the spidergon scheme and present an analytical evaluation of the average message latency in the architecture. We prove the validity of the analysis by comparing the model against the results produced by a discreteevent simulator.

Item Type:Conference Proceedings
Glasgow Author(s) Enlighten ID:Vanderbauwhede, Professor Wim
Authors: Moadeli, M., Sharabi, A., Vanderbauwhede, W.A., and Ould-Khaoua, M.
Subjects:Q Science > QA Mathematics > QA75 Electronic computers. Computer science
College/School:College of Science and Engineering > School of Computing Science
Publisher:IEEE Computer Society
Copyright Holders:Copyright © 2007 Institute of Electrical and Electronics Engineers
First Published:First published in the 21st Annual Conference on Advanced Networking and Applications, 2007. AINA '07
Publisher Policy:Reproduced in accordance with the copyright policy of the publisher.

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
389341A novel service-based system on a chip architecture using on chip networks with smart packets and dynamically reconfigurable logicWim VanderbauwhedeEngineering & Physical Sciences Research Council (EPSRC)GR/T03239/01Computing Science