Evaluation of Intrinsic Parameter Fluctuations on 45, 32 and 22nm Technology Node LP N-MOSFETs

Cheng, B., Roy, S., Brown, A., Millar, C. and Asenov, A. (2008) Evaluation of Intrinsic Parameter Fluctuations on 45, 32 and 22nm Technology Node LP N-MOSFETs. In: ESSDERC 2008: Proceedings of the 38th European Solid-State Device Research Conference. Series: Proceedings of the European Solid-State Device Research Conference. IEEE: New York, pp. 47-50. ISBN 978-1-4244-2363-7 (doi: 10.1109/ESSDERC.2008.4681695)

Abstract

The quantitative evaluation of the impact of key sources of statistical variability (SV) are presented for LP nMOSFETs corresponding to 45nm, 32nm and 22nm technology generation transistors with bulk, thin body (TB) SOI and double gate (DG) device architectures respectively. The simulation results indicate that TBSOI and DG are not only resistant to random dopant induced variability, but also are more tolerant to line edge roughness induced variability. Even two technology generations ahead from their bulk counterparts, DG MOSFETs will still have 4 times less variability than bulk devices

• Item Type: Book Sections
• Additional Information: 38th European Solid-State Device Research Conference Edinburgh, SCOTLAND, SEP 15-19, 2008 Series ISSN: 1930-8876
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Millar, Dr Campbell and Cheng, Dr Binjie and Roy, Professor Scott and Asenov, Professor Asen
• Authors: Cheng, B., Roy, S., Brown, A., Millar, C., and Asenov, A.
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Journal Name: Essderc 2008: Proceedings of the 38Th European Solid-State Device Research Conference
• Publisher: IEEE
• ISSN: 1930-8876
• ISBN: 978-1-4244-2363-7