Benchmarking of scaled InGaAs implant-free NanoMOSFETs

Kalna, K., Seoane, N., Garcia-Loureiro, A. J., Thayne, I. G. and Asenov, A. (2008) Benchmarking of scaled InGaAs implant-free NanoMOSFETs. IEEE Transactions on Electron Devices, 55(9), pp. 2297-2306. (doi:10.1109/TED.2008.927658)

Kalna, K., Seoane, N., Garcia-Loureiro, A. J., Thayne, I. G. and Asenov, A. (2008) Benchmarking of scaled InGaAs implant-free NanoMOSFETs. IEEE Transactions on Electron Devices, 55(9), pp. 2297-2306. (doi:10.1109/TED.2008.927658)

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Abstract

The potential performance of n-type implant-free (IF) III-V nanoMOSFETs with an In0.75Ga0.25As channel is studied using finite-element heterostructure Monte Carlo (MC) and parallel 3-D drift-diffusion (D-D) simulations. These devices, scaled to gate lengths of 30, 20, and 15 nm, are compared with the equivalent gate length In0.3Ga0.7As channel IF MOSFETs and with a state-of-the-art Si TriGate FinFET. The benchmarking study is based on careful calibration of the MC simulator against experimental transport data obtained from relevant delta-doped heterostructures with a high-kappa, gate dielectric. At 0.8-V supply voltage, the 30-nm gate length In0.7Ga0.25As channel IF III-V MOSFET is predicted to deliver a drive current of 2880 mu A/mu m and to have a subthreshold slope of 94.7 mV/dec compared with 2380 mu A/mu m for an equivalent gate length In0.3Ga0.7As channel IF MOSFET. When the In0.75Ga0.25As channel IF transistor is scaled to 20- and 15-nm gate lengths, the drive current increases to 3520 and 3605 mu A/mu m, featuring subthreshold slopes of 107.8 and 131.7 mV/dec, respectively. The threshold voltage variability induced by the discrete dopants in the delta-doped plane is studied using 3-D D-D simulations. The 30-, 20-, and 15-nm gate length In0.75Ga0.25As channel IF transistors exhibit threshold voltage standard deviations of 42, 58, and 61 mV, respectively, which are close to or lower than those observed in bulk Si MOSFETs with equivalent gate lengths

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Thayne, Professor Iain and Asenov, Professor Asen and Kalna, Dr Karol
Authors: Kalna, K., Seoane, N., Garcia-Loureiro, A. J., Thayne, I. G., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:IEEE Transactions on Electron Devices
Publisher:Institute of Electrical and Electronics Engineers
ISSN:0018-9383
Published Online:19 August 2008

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
452481Silicon compatible process modules for III-V electronic devices.Iain ThayneEngineering & Physical Sciences Research Council (EPSRC)EP/F002610/1Electronic and Nanoscale Engineering