A low damage Si3N4 sidewall spacer process for self-aligned sub-100 nm III-V MOSFETs

Li, X. , Hill, R.J.W., Zhou, H. P., Wilkinson, C.D.W. and Thayne, I.G. (2008) A low damage Si3N4 sidewall spacer process for self-aligned sub-100 nm III-V MOSFETs. Microelectronic Engineering, 85(5-6), pp. 996-999. (doi:10.1016/j.mee.2007.12.064)

Li, X. , Hill, R.J.W., Zhou, H. P., Wilkinson, C.D.W. and Thayne, I.G. (2008) A low damage Si3N4 sidewall spacer process for self-aligned sub-100 nm III-V MOSFETs. Microelectronic Engineering, 85(5-6), pp. 996-999. (doi:10.1016/j.mee.2007.12.064)

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Publisher's URL: http://dx.doi.org/10.1016/j.mee.2007.12.064

Abstract

This paper investigates a low damage reactive ion etch (RIE) process to make thin silicon nitride sidewall spacers for the fabrication of self-aligned sub-100 nm gate length III-V metal-oxide-semiconductor field-effect-transistors (MOSFETs). Self-alignment is essential to minimize the contribution to the parasitic series source/drain resistance (RSD) from the access region between the ohmic contact and the gate, whilst retaining the overall electrostatic integrity of the device. In this work, a blanket Si3N4 was deposited by room temperature inductively coupled plasma chemical vapour deposition (ICP-CVD) and etched by reactive ion etching in a SF6/N-2 based chemistry. Conditions were optimised to ensure low damage to the underlying device layer stack. This process has successfully produced thin Si3N4 spacers for fabricating self-aligned GaAs MOSFETs. The sheet resistance of III-V MOSFET materials was monitored as a function of etch parameters to assess the impact of damage related effects on the electronic characteristics of the underlying material. The etching profile and the sheet resistance of the device layer structures were characterised by using scanning electronic microscope (SEM) and sonogage, respectively.

Item Type:Articles
Additional Information:33rd International Conference on Micro- and Nano-Engineering Copenhagen, DENMARK, SEP 23-26, 2007
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Zhou, Dr Haiping and Thayne, Professor Iain and Hill, Mr Richard and Wilkinson, Professor Christopher and Li, Dr Xu
Authors: Li, X., Hill, R.J.W., Zhou, H. P., Wilkinson, C.D.W., and Thayne, I.G.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Microelectronic Engineering
ISSN:0167-9317

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