Low damage ashing and etching processes for ion implanted resist and Si3N4 removal by ICP and RIE methods

Li, X. , Zhou, H.P., Abrokwah, J., Zurcher, P., Rajagopalan, K., Liu, W., Gregory, R., Passlack, M. and Thayne, I.G. (2008) Low damage ashing and etching processes for ion implanted resist and Si3N4 removal by ICP and RIE methods. Microelectronic Engineering, 85(5-6), pp. 966-968. (doi: 10.1016/j.mee.2007.12.056)

Abstract

This paper presents a low damage, ion implantation mask removal process where the ion implantation mask, consisting of photoresist and Si3N4 deposited by room temperature ICP-CVD (inductively coupled plasma chemical vapour deposition), has been successfully removed through combining ICP (inductively coupled plasma) O-2 plasma ashing and SF6/O-2 reactive ion etching (RIE) of the Si3N4. The process leaves a clean, smooth post-etching surface with rms roughness of less than I nm, on a device quality, high-kappa GaxGdyOz (GGO) oxide layer for the fabrication of III-V metal-oxide-semiconductor field-effect-transistors (MOSFETs). Equally importantly, no etch induced damage occurs in the underlying high mobility III-V semiconductor layers. The post-etched GGO surface roughness and electrical transport properties of the underlying device layer structures were characterised by atomic force microscopy (AFM) and sonogage, respectively.

• Item Type: Articles
• Additional Information: 33rd International Conference on Micro- and Nano-Engineering Copenhagen, DENMARK, SEP 23-26, 2007
• Status: Published
• Refereed: Yes
• Glasgow Author(s) Enlighten ID: Zhou, Dr Haiping and Thayne, Prof Iain and Li, Dr Xu
• Authors: Li, X., Zhou, H.P., Abrokwah, J., Zurcher, P., Rajagopalan, K., Liu, W., Gregory, R., Passlack, M., and Thayne, I.G.
• College/School: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Journal Name: Microelectronic Engineering
• ISSN: 0167-9317