Matching the transconductance characteristics of CMOS ISFET arrays by removing trapped charge

Milgrew, M. J. and Cumming, D. R. S. (2008) Matching the transconductance characteristics of CMOS ISFET arrays by removing trapped charge. IEEE Transactions on Electron Devices, 55(4), pp. 1074-1079. (doi:10.1109/TED.2008.916680)

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Publisher's URL: http:/dx.doi.org/10.1109/TED.2008.916680

Abstract

This paper presents an approach for matching the transconductance characteristics of CMOS ISFET arrays by removing trapped charge. We describe how to design arrays of floating-gate ISFETs so that ultraviolet (UV) radiation and bulk-substrate biasing can be used to remove the random amount of trapped charge that accumulates on the gates during fabrication. The approach is applied directly to a prototype single-chip 2 x 2 array of ISFETs, which is designed and fabricated in a standard 0.35-mu m CMOS process. By considering the transconductance characteristics of the 2 x 2 array before and after UV exposure, it is shown that the response can be matched after 10 h and that the ISFET threshold voltages converge to an equilibrium value of approximately -1 V. After matching, it is found that the ISFET array has a measured sensitivity of 46 mV/pH and can successfully image a change in the pH of a homogeneous electrolyte solution

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Cumming, Professor David and Milgrew, Dr Mark
Authors: Milgrew, M. J., and Cumming, D. R. S.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:IEEE Transactions on Electron Devices
Publisher:Institute of Electrical and Electronics Engineers
ISSN:0018-9383
Published Online:21 March 2008

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
400041Electronics Design Centre for Heterogeneous SystemsDavid CummingEngineering & Physical Sciences Research Council (EPSRC)EP/D501288/1ENG - ENGINEERING ELECTRONICS & NANO ENG