Investigation into effects of device variability on CMOS layout motifs

Paluchowski, S. H., Cheng, B., Roy, S., Asenov, A. and Cumming, D. R. S. (2008) Investigation into effects of device variability on CMOS layout motifs. Electronics Letters, 44(10), pp. 626-627. (doi:10.1049/el:20080447)

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Publisher's URL: http://dx.doi.org/10.1049/el:20080447

Abstract

Sub-circuit motifs are proposed as a methodology for simulating the performance of sub-45 nm circuits exhibiting atomistic device fluctuations. Motifs allow the reduction of the problem space and create a standard motif library as a step in the design hierarchy for logic circuits. Device variability information from 3D simulation results is used that is incorporated into families of BSIM4 models. It is demonstrated how a thorough understanding of circuit behaviour can be obtained and the impact on current drive is illustrated by examining the effect of additional parasitic resistances

Item Type:Articles
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Cumming, Professor David and Cheng, Dr Binjie and Asenov, Professor Asen
Authors: Paluchowski, S. H., Cheng, B., Roy, S., Asenov, A., and Cumming, D. R. S.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Electronics Letters
Publisher:The Institution of Engineering & Technology
ISSN:0013-5194
ISSN (Online):1350-911X

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