Two methods of realising 10 nm T-gate lithography

Bentley, S., Li, X. , Moran, D.A.J. and Thayne, I.G. (2009) Two methods of realising 10 nm T-gate lithography. Microelectronic Engineering, 86(4-6), pp. 1067-1070. (doi:10.1016/j.mee.2008.12.029)

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Abstract

This paper presents two separate methods for the fabrication of 10 nm footprint T-gates using a two-step gate process. We examine the limits of lithographic and pattern transfer processes using the exposure of ZEP520A resist by electron beam lithography, suitable development processes and subsequent pattern transfer by SF6/N-2 reactive ion etching of a silicon nitride layer on III-V substrates. In a second process, the dimensions of a larger initial feature are reduced using the deposition and etching of conformal silicon nitride. Both processes have yielded metallised gates with a footprint as small as 10 nm and are suitable for incorporation into a HEMT process flow.

Item Type:Articles
Additional Information:Paper presented at the 34th International Conference on Micro- and Nano-Engineering (MNE 2008), Athens, Greece, 15-18 September 2008.
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Li, Dr Xu and Thayne, Professor Iain and Bentley, Dr Steven and Moran, Dr David
Authors: Bentley, S., Li, X., Moran, D.A.J., and Thayne, I.G.
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Microelectronic Engineering
Publisher:Elsevier
ISSN:0167-9317
ISSN (Online):1873-5568
Published Online:24 December 2008

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Project CodeAward NoProject NamePrincipal InvestigatorFunder's NameFunder RefLead Dept
450861Ultra short gate length diamond FETs for high power/high frequency applicationsDavid MoranEngineering & Physical Sciences Research Council (EPSRC)EP/E054668/1ENG - ENGINEERING ELECTRONICS & NANO ENG