A nanoanalytical investigation of high-k dielectric gate stacks for GaAs based MOSFET devices

Longo, P., Craven, A.J., Holland, M.C., Moran, D.A.J. and Thayne, I.G. (2009) A nanoanalytical investigation of high-k dielectric gate stacks for GaAs based MOSFET devices. Microelectronic Engineering, 86(3), pp. 214-217. (doi: 10.1016/j.mee.2008.08.013)

Full text not currently available from Enlighten.

Abstract

In this paper a quantitative determination of the elemental distributions across a similar to 10 nm Ga2O3/GdGaO layer with Pt metal gate cap on top of an InGaAs/AlGaAs/GaAs substrate is presented. Some effects of annealing on the elemental distribution across the Ga2As/Ga(2)O(3)GGaO oxide layer are described. The paper also discusses the analysis of the interface GaAs/Ga2O3/GGO at a sub-nm level by high-resolution HAADF STEM imaging.

Item Type:Articles
Additional Information:The Fourth IEEE International Symposium on Advanced Gate Stack Technoiogy (ISAGST 2007)
Keywords:Annealing effects, device, devices, EELS spectrum imaging, engineering, ga and gd mixed dielectric oxide layers, GaAs, GaAs based mosfet devices, layer, mosfet, optics, oxide, oxide layer, physics, science, stem imaging compositional analysis, substrate, TEM analysis, top
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Thayne, Prof Iain and Longo, Dr Paolo and Moran, Professor David and Craven, Professor Alan and Holland, Dr Martin
Authors: Longo, P., Craven, A.J., Holland, M.C., Moran, D.A.J., and Thayne, I.G.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Microelectronic Engineering
ISSN:0167-9317

University Staff: Request a correction | Enlighten Editors: Update this record