Lithography scaling issues associated with III-V MOSFETs

Ignatova, O., Thoms, S. , Jansen, W., Macintyre, D.S. and Thayne, I.G. (2010) Lithography scaling issues associated with III-V MOSFETs. Microelectronic Engineering, 87(5-8), pp. 1049-1051. (doi: 10.1016/j.mee.2009.11.093)

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In this work we investigate fabrication issues associated with scaling down the gate length and source drain contact separation of a III-V MOSFET. We used high resolution electron-beam lithography and lift-off for gate and ohmic contact patterning to fabricate gate-last lithographically-aligned MOSFETs. This work considers the effect of variations in resist thickness on gate lengths and also the fabrication of long narrow gaps using electron-beam lithography. The study showed that the effect of resist thickness variation on metal linewidth is insignificant. A difference of around 2-3 nm was found between PtAu line-widths fabricated using 150 and 280 nm thick resist. A VB6 lithography tool was found to be useful for linewidth measurements. We showed that the choice of resist is critical to gap formation, and that PMMA is not well suited to this task.

Item Type:Articles
Additional Information:The 35th International Conference on Micro- and Nano-Engineering (MNE)
Keywords:Channel, E-beam, electron beam, electron-beam lithography, fabrication, GAAS, lift-off, lithography, mosfet, mosfets, physics, PMMA, poly(methylmethacrylate), resist thickness variation
Glasgow Author(s) Enlighten ID:Thayne, Prof Iain and Thoms, Dr Stephen and Macintyre, Dr Douglas
Authors: Ignatova, O., Thoms, S., Jansen, W., Macintyre, D.S., and Thayne, I.G.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Microelectronic Engineering

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