III-V MOSFETs for digital applications with silicon co-integration

Kalna, K. et al. (2008) III-V MOSFETs for digital applications with silicon co-integration. In: 7th International Conference on Advanced Semiconductor Devices and Microsystems, Smolenice, Slovakia, 12-16 October 2008, pp. 39-46. ISBN 9781424423255 (doi:10.1109/ASDAM.2008.4743354)

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Abstract

The prospect or the introduction of III-V semiconductors into the channel of n-type MOSFETs and thus replace Si with a high mobility material for 22 nm technology generation and beyond is examined in detail. The so-called implant free (IF) III-V MOSFET architecture option is presented showing a fabricated n-type IF demonstrator suitable for scaling. We then focus on a prediction of the potential performance of III-V MOSFETs through physically-based Monte Carlo (MC) device simulations. An implanted, n-type III-V MOSFETs based on In0.3Ga0.7As channel is investigated when scaled from a gate length of 30 nm to 20 nm and 15 nm. The impact of decisive scattering mechanisms operative at the dielectric/semiconductor interface is discussed. We also simulate the IF devices with low (In0.3Ga0.7As) and high (In(0.75)Ga(0.25)AS) Indium content channel scaled to gate lengths of 30, 20 and 15 nm with equivalent layer thicknesses. The IF architecture is found to deliver a high drive current because of the highly efficient injection of electrons into the channel and because of very low access resistances. However the low Indium content channel IF transistor is not able to further increase its drive current when scaled to the 15 nm gate length. Therefore, we examine also the performance of high Indium channel transistors which delivers a steady increase in the device performance down to the 15 nm gate length.

Item Type:Conference Proceedings
Keywords:Access, benchmarking, channel, channel mosfets, cmos applications, device, devices, engineering, gate-length, generation, high-performance, impact, injection, layer, logic applications, mechanisms, mobility, monte carlo, monte-carlo simulations, mosfet, mosfets, nano-mosfets, nm, performance, prediction, resistance, scattering, semiconductor, semiconductors, si, silicon, simulation, technologies, technology, thickness, transistor, transistors
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Longo, Dr Paolo and Li, Dr Xu and Zhou, Dr Haiping and Thayne, Professor Iain and Macintyre, Dr Douglas and Long, Professor Andrew and Thoms, Dr Stephen and Asenov, Professor Asen and Paterson, Dr Gary and Ayubi-Moak, Mr Jason and Craven, Professor Alan and Hill, Mr Richard and Stanley, Professor Colin and Kalna, Dr Karol and Holland, Dr Martin
Authors: Kalna, K., Asenov, A., Ayubi-Moak, J.S., Craven, A.J., Droopad, R., Hill, R., Holland, M.C., Li, X., Long, A.R., Longo, P., Macintyre, D., Passlack, M., Paterson, G., Stanley, C.R., Thoms, S., Zhou, H., and Thayne, I.G.
College/School:College of Science and Engineering > School of Physics and Astronomy
College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Publisher:IEEE Computer Society
ISBN:9781424423255

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