EFTEM and EELS SI: tools for investigating the effects of etching processes for III-V MOSFET devices

Longo, P., Scott, J. , Craven, A.J., Hill, R.J.W. and Thayne, I.G. (2008) EFTEM and EELS SI: tools for investigating the effects of etching processes for III-V MOSFET devices. Journal of Physics: Conference Series, 126(1), 012053. (doi: 10.1088/1742-6596/126/1/012053)

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Abstract

High quality oxides layers are now available for MOSFETs on GaAs. For successful devices, suitable process schemes are required. In this paper we show an investigation of an etching process on a GaAs/Ga2O3/GGO dielectric gate stack. This investigation has been carried out using EFTEM and EELS SI. EFTEM provides a quick analysis on the structure while EELS SI offers much better resolution and the possibility to quantitatively characterize the material.

Item Type:Articles
Keywords:Device, devices, EELS, electron-microscopy, England, etching, GaAs, layer, layers, microscopy, MOSFET, MOSFETS, oxide, physics, resolution, science, SI
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Thayne, Prof Iain and Longo, Dr Paolo and Scott, Dr Jamie and Hill, Mr Richard and Craven, Professor Alan
Authors: Longo, P., Scott, J., Craven, A.J., Hill, R.J.W., and Thayne, I.G.
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Q Science > QC Physics
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
College of Science and Engineering > School of Physics and Astronomy
Journal Name:Journal of Physics: Conference Series
ISSN:1742-6588
ISSN (Online):1742-6596
ISBN:1742-6588
Published Online:25 September 2008

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