Effect of interface state trap density on the characteristics of n-type, enhancement-mode, implant-free In0.3Ga0.7As MOSFETs

Ayubi-Moak, J.S., Benbakhti, B., Kalna, K., Paterson, G.W., Hill, R., Passlack, M., Thayne, I.G. and Asenov, A. (2009) Effect of interface state trap density on the characteristics of n-type, enhancement-mode, implant-free In0.3Ga0.7As MOSFETs. Microelectronic Engineering, 86(7-9), pp. 1564-1567. (doi:10.1016/j.mee.2009.03.024)

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Abstract

The effect of interface state trap density, D-it, on the device characteristics of n-type, enhancement-mode, implant-free (IF) In0.3Ga0.7As MOSFETs [1,2] has been investigated using a commercial drift-diffusion (DD) device simulation tool. Methodology has been developed to include arbitrary D-it, distributions in the input simulation decks to more accurately fit the measured subthreshold characteristics of recently reported 1.0 mu m gate length IF In0.3Ga0.7As MOSFETs [3]. The impact of interface states on a scaled 30 nm gate length IF MOSFET is also reported.

Item Type:Articles
Keywords:Density, device, drift-diffusion, engineering, enhancement-mode, Gaas, Iii-V mosfets, impact, interface state trap density, mobility, mosfet, mosfets, physics, science, simulation
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Thayne, Professor Iain and Asenov, Professor Asen and Benbakhti, Dr Brahim and Hill, Mr Richard and Ayubi-Moak, Mr Jason and Kalna, Dr Karol
Authors: Ayubi-Moak, J.S., Benbakhti, B., Kalna, K., Paterson, G.W., Hill, R., Passlack, M., Thayne, I.G., and Asenov, A.
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Journal Name:Microelectronic Engineering
Publisher:Elsevier
ISSN:0167-9317
ISSN (Online):1873-5568
Published Online:11 March 2009

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