A low damage RIE process for the fabrication of cmpound semiconductor based transistors wtih sub-100nm tungsten gates

Li, X., Cao, X., Zhou, H., Wilkinson, C., Thoms, S., Macintyre, D., Holland, M. and Thayne, I. (2005) A low damage RIE process for the fabrication of cmpound semiconductor based transistors wtih sub-100nm tungsten gates. In: 31st International Conference on Micro and Nano-Engineering 2005, Vienna, Austria,

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Item Type:Conference Proceedings
Keywords:Damage, Fabrication, Gate, Rie, Semiconductor, Transistors
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Zhou, Dr Haiping and Thayne, Professor Iain and Thoms, Dr Stephen and Li, Dr Xiang and Wilkinson, Professor Christopher and Macintyre, Dr Douglas and Holland, Dr Martin
Authors: Li, X., Cao, X., Zhou, H., Wilkinson, C., Thoms, S., Macintyre, D., Holland, M., and Thayne, I.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering

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