Low damage dry etching processes for the fabrication of compound semiconductor based transistors with sub-100nm tungsten gates

Li, X. , Zhou, H., Cao, X., Wilkinson, C.D.W. and Thayne, I.G. (2006) Low damage dry etching processes for the fabrication of compound semiconductor based transistors with sub-100nm tungsten gates. In: UK III-V Compound Semiconductors 2006, Sheffield, UK,

Full text not currently available from Enlighten.


Item Type:Conference Proceedings
Keywords:Cells, Compound Semiconductor, Damage, Dry Etching, Electron, Electron-Microscopy, Fabrication, GAAS, Gate, Gates, HEMT, Intermediate Band, Losses, Low Damage, MOSFET, MOSFETS, Semiconductor, Semiconductors, Solar Cell, Spectroscopy, System, Systems, Technology, Transistors, Tra
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Li, Dr Xu and Zhou, Dr Haiping and Thayne, Professor Iain and Wilkinson, Professor Christopher
Authors: Li, X., Zhou, H., Cao, X., Wilkinson, C.D.W., and Thayne, I.G.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Publisher:IOP/EPSRC

University Staff: Request a correction | Enlighten Editors: Update this record