A low damage RIE SiN sidewall spacer process for self-aligned sub-100nm III-V MOSFETs

Li, X. , Hill, R., Zhou, H., Wilkinson, C.D.W. and Thayne, I.G. (2006) A low damage RIE SiN sidewall spacer process for self-aligned sub-100nm III-V MOSFETs. In: UK III-V Compound Semiconductors 2006, Sheffield, UK,

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Item Type:Conference Proceedings
Keywords:Cells, Compound Semiconductor, Damage, Dry Etching, Electron, Electron-Microscopy, Fabrication, GAAS, Gates, HEMT, III-V MOSFET, III-V MOSFETS, Intermediate Band, Losses, Low Damage, MOSFET, MOSFETS, Rie, Self-Aligned, Semiconductor, Semiconductors, Solar Cell, Spacer, Spectros
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Li, Dr Xu and Zhou, Dr Haiping and Thayne, Professor Iain and Hill, Mr Richard and Wilkinson, Professor Christopher
Authors: Li, X., Hill, R., Zhou, H., Wilkinson, C.D.W., and Thayne, I.G.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Publisher:IOP/EPSRC

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