Impact of Fermi level pinning at polysilicon gate grain boundaries on nano-MOSFET variability:A 3-D simulation study

Brown, A., Roy, G. and Asenov, A. (2006) Impact of Fermi level pinning at polysilicon gate grain boundaries on nano-MOSFET variability:A 3-D simulation study. In: 34th European Solid State Devices Research Conference, Montreux, Switzerland, pp. 451-454.

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Item Type:Conference Proceedings
Keywords:6T SRAM, Design, Device, Devices, Fluctuations, Gate, Impact, Level, Simulation, SRAM, Technology
Status:Published
Refereed:Yes
Glasgow Author(s) Enlighten ID:Roy, Dr Gareth and Brown, Mr Andrew and Asenov, Professor Asen
Authors: Brown, A., Roy, G., and Asenov, A.
College/School:College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Publisher:IEEE

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